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The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com
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HM66AQB36104/HM66AQB18204 HM66AQB9404/HM66AQB8404
36-Mbit QDR II SRAM 4-word Burst
TM
ADE-203-1331B (Z) Preliminary Rev. 0.2 Jan. 14, 2003 Description
The HM66AQB36104 is a 1,048,576-word by 36-bit, the HM66AQB18204 is a 2,097,152-word by 18-bit, the HM66AQB9404 is a 4,194,304-word by 9-bit, and the HM66AQB8404 is a 4,194,304-word by 8-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS sixtransistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K) and are latched on the positive edge of K and K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
Note: QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, Micron Technology, Inc., NEC, Samsung, and Hitachi. Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specifications.
HM66AQB36104/18204/9404/8404
Features
* 1.8 V 0.1 V power supply for core (VDD) * 1.4 V to VDD power supply for I/O (VDDQ) * DLL circuitry for wide output data valid window and future frequency scaling * Separate independent read and write data ports with concurrent transactions * 100% bus utilization DDR read and write operation * Four-tick burst for reduced address frequency * Two input clocks (K and K) for precise DDR timing at clock rising edges only * Two output clocks (C and C) for precise flight time and clock skew matching-clock and data delivered together to receiving device * Internally self-timed write control * Clock-stop capability with s restart * User programmable impedance output * Fast clock cycle time: 3.0 ns (333 MHz)/3.3 ns (300 MHz)/4.0 ns (250 MHz)/ 5.0 ns (200 MHz)/6.0 ns (167 MHz) * Simple control logic for easy depth expansion * JTAG boundary scan
Ordering Information
Type No. HM66AQB36104BP-30 HM66AQB36104BP-33 HM66AQB36104BP-40 HM66AQB36104BP-50 HM66AQB36104BP-60 HM66AQB18204BP-30 HM66AQB18204BP-33 HM66AQB18204BP-40 HM66AQB18204BP-50 HM66AQB18204BP-60 HM66AQB9404BP-30 HM66AQB9404BP-33 HM66AQB9404BP-40 HM66AQB9404BP-50 HM66AQB9404BP-60 HM66AQB8404BP-30 HM66AQB8404BP-33 HM66AQB8404BP-40 HM66AQB8404BP-50 HM66AQB8404BP-60 Organization 1-M word x 36-bit Cycle time 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns Clock frequency 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Package Plastic FBGA 165-pin (BP-165A)
2-M word x 18-bit
4-M word x 9-bit
4-M word x 8-bit
Rev.0.2, Jan. 2003, page 2 of 31
HM66AQB36104/18204/9404/8404
Pin Arrangement (HM66AQB36104) 165PIN-BGA
1 A B C D E F G H J K L M N P R CQ Q27 D27 D28 Q29 Q30 D30 DOFF D31 Q32 Q33 D33 D34 Q35 TDO 2 VSS Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 NC D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 BW1 BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 SA 10 NC Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
(Top view)
Pin Arrangement (HM66AQB18204) 165PIN-BGA
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 VSS Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 SA D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 NC NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
(Top view)
Rev.0.2, Jan. 2003, page 3 of 31
HM66AQB36104/18204/9404/8404
Pin Arrangement (HM66AQB9404) 165PIN-BGA
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 VSS NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 SA NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NC NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC D2 NC NC VREF Q1 NC NC NC NC D8 TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC Q8 TDI
(Top view)
Pin Arrangement (HM66AQB8404) 165PIN-BGA
1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 VSS NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 SA NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC NW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
(Top view)
Rev.0.2, Jan. 2003, page 4 of 31
HM66AQB36104/18204/9404/8404
Pin Descriptions
Name SAn I/O type Descriptions Input Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. Ball 2A is reserved for the next higher-order address input on future devices. All transactions operate on burst-of-four words (two clock periods of bus activity). These inputs are ignored when device is deselected. Synchronous read: When low, this input causes the address inputs to be registered and a READ cycle to be initiated. This input must meet setup and hold times around the rising edge of K, and is ignored on the subsequent rising edge of K. Synchronous write: When low, this input causes the address inputs to be registered and a WRITE cycle to be initiated. This input must meet setup and hold times around the rising edge of K, and is ignored on the subsequent rising edge of K. Synchronous byte writes (nibble writes on x8): When low, these inputs cause their respective byte or nibble to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and K for each of two rising edges comprising the WRITE cycle. See Byte Write Truth Table for signal to data relationship. Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of K. K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. Output clock: This clock pair provides a user-controlled means of tuning device output data. The rising edge of C is used as the output timing reference for second and fourth output data. The rising edge of C is used as the output reference for first and third output data. Ideally, C is 180 degrees out of phase with C. C and C may be tied high to force the use of K and K as the output reference clocks instead of having to provide C and C clocks. If tied high, C and C must remain high and not to be toggled during device operation. DLL disable: When low, this input causes the DLL to be bypassed for stable, low frequency operation. Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. Q and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this ball to ground. Alternately, this ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to VSS or left unconnected. IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the JTAG function is not used in the circuit. IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG function is not used in the circuit.
R
Input
W
Input
NWn BW BWn
Input
K, K
Input
C, C
Input
DOFF ZQ
Input Input
TMS TDI TCK
Input Input
Rev.0.2, Jan. 2003, page 5 of 31
HM66AQB36104/18204/9404/8404
Name I/O type Descriptions Synchronous data inputs: Input data must meet setup and hold times around the rising edges of K and K during WRITE operations. See Pin Arrangement figures for ball site location of individual signals. The x8 device uses D0 to D7. Remaining signals are NC. The x9 device uses D0 to D8. Remaining signals are NC. The x18 device uses D0 to D17. Remaining signals are NC. The x36 device uses D0 to D35. NC signals are read in the JTAG scan chain as the logic level applied to the ball site. D0 to Dn Input
CQ, CQ
Output Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tri-states. Output IEEE 1149.1 test output: 1.8 V I/O level.
TDO
Q0 to Qn Output Synchronous data outputs: Output data is synchronized to the respective C and C, or to the respective K and K rising edges if C and C are tied high. This bus operates in response to R commands. See Pin Arrangement figures for ball site location of individual signals. The x8 device uses Q0 to Q7. Remaining signals are NC. The x9 device uses Q0 to Q8. Remaining signals are NC. The x18 device uses Q0 to Q17. Remaining signals are NC. The x36 device uses Q0 to Q35. NC signals are read in the JTAG scan chain as the logic level applied to the ball site. VDD VDDQ VSS VREF NC Supply Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range. Supply Power supply: Isolated output buffer supply. Nominally 1.5 V. 1.8 V is also permissible. See DC Characteristics and Operating Conditions for range. Supply Power supply: Ground HSTL input reference voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. No connect: These signals are internally connected and appear in the JTAG scan chain as the logic level applied to the ball sites. These signals may be connected to ground to improve package heat dissipation.
Note:
1. All power supply and ground balls must be connected for proper operation of the device.
Rev.0.2, Jan. 2003, page 6 of 31
HM66AQB36104/18204/9404/8404
Block Diagram (HM66AQB36104)
Address 18
R W
Address registry and logic
18
K
W BW0 BW1 BW2 BW3
D0 to D35 36 Data registry and logic 72 MUX 72 36 Q0 to Q35
Output register
Write register
Output select
Output buffer
72
Memory array
144
Sense amps
Write driver
72 MUX
2
CQ,
R
K K
CQ
C
K
C, C or K, K
Block Diagram (HM66AQB18204)
Address 19
R W
Address registry and logic
19
K
W BW0 BW1
18 D0 to D17 36 Data registry and logic MUX 36 18 Q0 to Q17
Output register
Write register
Output select
Output buffer
R
36
Memory array
72
Sense amps
Write driver
36 MUX
2
CQ,
CQ
K K C
K
C, C or K, K
Rev.0.2, Jan. 2003, page 7 of 31
HM66AQB36104/18204/9404/8404
Block Diagram (HM66AQB9404)
Address 20
R W
K
Address registry and logic
20
W BW
18 9 D0 to D8 Data registry and logic
Write register Sense amps Write driver
MUX 18
Output register Output select Output buffer
9 36
Q0 to Q8
R
K
18
Memory array
18 MUX
2
CQ,
CQ
C C, C or K, K
K
K
Block Diagram (HM66AQB8404)
Address 20
R W
Address registry and logic
20
K
W NW0 NW1
8 D0 to D7 16 Data registry and logic MUX 16 8 Q0 to Q7
Output register
Write register
Output select
Output buffer
R
16
Memory array
32
Sense amps
Write driver
16 MUX
2
CQ,
CQ
K K C
K
C, C or K, K
Rev.0.2, Jan. 2003, page 8 of 31
HM66AQB36104/18204/9404/8404
Truth Table
Operation WRITE cycle Load address, input write data on two consecutive K and K rising edges
*8
K LH
R H
*7
W L
*8
D or Q Data in Input data Input clock DA(A+0) K(t+1) DA(A+1) K(t+1) DA(A+2) K(t+2) DA(A+3) K(t+2)
READ cycle Load address, read data on two consecutive C and C rising edges
LH
L
x
Data out Output QA(A+0) data Output C(t+1) clock QA(A+1) C(t+2) QA(A+2) C(t+2) QA(A+3) C(t+3)
NOP (No operation) STANDBY (Clock stopped)
LH
H
H x
D = x or Q = High-Z Previous state
Stopped x
Notes: 1. H: high level, L: low level, x: don't care, : rising edge. 2. Data inputs are registered at K and K rising edges. Data outputs are delivered at C and C rising edges, except if C and C are high, then data outputs are delivered at K and K rising edges. 3. R and W must meet setup/hold times around the rising edges (low to high) of K and are registered at the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. It is recommended that (K) = /(K) = (C) = /(C) when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 7. If this signal was low to initiate the previous cycle, this signal becomes a "don't care" for this operation; however, it is strongly recommended that this signal be brought high, as shown in the truth table. 8. This signal was high on previous K clock rising edge. Initiating consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The device will ignore the second request.
Rev.0.2, Jan. 2003, page 9 of 31
HM66AQB36104/18204/9404/8404
Byte Write Truth Table
(HM66AQB36104)
Operation Write D0 to D35 K LH Write D0 to D8 LH Write D9 to D17 LH Write D18 to D26 LH Write D27 to D35 LH Write nothing LH K LH LH LH LH LH LH BW0 0 0 0 0 1 1 1 1 1 1 1 1 BW1 0 0 1 1 0 0 1 1 1 1 1 1 BW2 0 0 1 1 1 1 0 0 1 1 1 1 BW3 0 0 1 1 1 1 1 1 0 0 1 1
Notes: 1. H: high level, L: low level, : rising edge. 2. Assumes a WRITE cycle was initiated. BW0 to BW3 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied.
(HM66AQB18204)
Operation Write D0 to D17 K LH Write D0 to D8 LH Write D9 to D17 LH Write nothing LH K LH LH LH LH BW0 0 0 0 0 1 1 1 1 BW1 0 0 1 1 0 0 1 1
Notes: 1. H: high level, L: low level, : rising edge. 2. Assumes a WRITE cycle was initiated. BW0 and BW1 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied.
Rev.0.2, Jan. 2003, page 10 of 31
HM66AQB36104/18204/9404/8404
(HM66AQB9404)
Operation Write D0 to D8 K LH Write nothing LH K LH LH BW 0 0 1 1
Notes: 1. H: high level, L: low level, : rising edge. 2. Assumes a WRITE cycle was initiated. BW can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied.
(HM66AQB8404)
Operation Write D0 to D7 K LH Write D0 to D3 LH Write D4 to D7 LH Write nothing LH K LH LH LH LH NW0 0 0 0 0 1 1 1 1 NW1 0 0 1 1 0 0 1 1
Notes: 1. H: high level, L: low level, : rising edge. 2. Assumes a WRITE cycle was initiated. NW0 and NW1 can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied.
Rev.0.2, Jan. 2003, page 11 of 31
HM66AQB36104/18204/9404/8404
Bus Cycle State Diagram
4=L
Always LOAD NEW READ ADDRESS; R_Count = 0; R_Init = 1 READ DOUBLE; R_Count = R_Count+2
Always INCREMENT READ ADDRESS BY TWO *1 R_Init = 0 R_Count = 2
4=H
READ PORT NOP R_Init = 0
4 = L & R_Count = 4
Supply voltage provided
4 = H & R_Count = 4
POWER UP
9 = H & W_Count = 4
Supply voltage provided
9 = L & W_Count = 4
LOAD NEW WRITE ADDRESS; W_Count = 0 Always WRITE DOUBLE; W_Count = W_Count+2
Always INCREMENT WRITE ADDRESS BY TWO *1 W_Count = 2
9=H
WRITE PORT NOP
9=L R_Init = 0
Notes: 1. The address is concatenated with two additional internal LSBs to facilitate burst operation. The address order is always fixed as: xxx...xxx+0, xxx...xxx+1, xxx...xxx+2, xxx...xxx+3. Bus cycle is terminated at the end of this sequence (burst count = 4). 2. Read and write state machines can be active simultaneously. Read and write cannot be simultaneously initiated. Read takes precedence. 3. State machine control timing is controlled by K.
Rev.0.2, Jan. 2003, page 12 of 31
HM66AQB36104/18204/9404/8404
Absolute Maximum Ratings
Parameter Input voltage on any ball Input/output voltage Core supply voltage Output supply voltage Junction temperature Storage temperature Symbol VIN VI/O VDD VDDQ Tj TSTG Rating -0.5 to VDD + 0.5 (2.9 V max.) -0.5 to VDDQ + 0.5 (2.9 V max.) -0.5 to 2.9 -0.5 to VDD +125 (max) -55 to +125 Unit V V V V C C Notes 1, 4 1, 4 1, 4 1, 4
Notes: 1. All voltage is referenced to VSS. 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.9 V, whatever the instantaneous value of VDDQ.
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Power supply voltage -- core Power supply voltage -- I/O Input reference voltage -- I/O Input high voltage Input low voltage Symbol VDD VDDQ VREF VIH (DC) VIL (DC) Min 1.7 1.4 0.68 VREF + 0.1 -0.3 Typ 1.8 1.5 0.75 Max 1.9 VDD 0.95 VDDQ + 0.3 VREF - 0.1 Unit V V V V V 1 2, 3 2, 3 Notes
Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF. 2. VREF = 0.75 V (typ). 3. Overshoot: VIH (AC) VDD + 0.7 V for t tKHKH/2 Undershoot: VIL (AC) -0.5 V for t tKHKH/2 Power-up: VIH VDDQ + 0.3 V and VDD 1.7 V and VDDQ 1.4 V for t 200 ms During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min).
Rev.0.2, Jan. 2003, page 13 of 31
HM66AQB36104/18204/9404/8404
DC Characteristics (Ta = 0 to +70C, VDD = 1.8 V 0.1 V)
HM66AQB36104/HM66AQB18204 HM66AQB9404/HM66AQB8404 -30 Parameter Operating supply current (READ / WRITE) Symbol Typ Max -33 -40 -50 -60 Unit Notes
(x8 / x9 / x18) IDD (x36) IDD
TBD 525 TBD 710
475 640
400 545
330 445
280 380
mA mA
Standby supply current (NOP)
(x8 / x9 / x18) ISB1 (x36) ISB1
TBD 255 TBD 265
235 245
200 210
170 180
145 155
mA mA
Notes: 1. 2. 3. 4. 5.
All inputs (except ZQ, VREF) are held at either VIH or VIL. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. Typical values are measured at VDD = 1.8 V, VDDQ = 1.5 V, Ta = +25C, and tKHKH = 6 ns. Operating supply currents are measured at 100% bus utilization. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed.
Parameter Input leakage current
Symbol Min ILI VOH (Low) VOH -2 -2 VDDQ - 0.2 VDDQ/2 - 0.08 VSS VDDQ/2 - 0.08
Max 2 2 VDDQ VDDQ/2 + 0.08 0.2 VDDQ/2 + 0.08
Unit Test conditions Notes A A V V V V |IOH| 0.1 mA Notes1 IOL 0.1 mA Notes2 8 9 3, 4 3, 4 3, 4 3, 4 5, 7 6, 7
Output leakage current ILO Output high voltage
Output low voltage
VOL (Low) VOL
Output "High" current Output "Low" current
IOH IOL
(VDDQ/2)/(RQ/5 + 10%) (VDDQ/2)/(RQ/5 - 10%) mA (VDDQ/2)/(RQ/5 - 10%) (VDDQ/2)/(RQ/5 + 10%) mA
Rev.0.2, Jan. 2003, page 14 of 31
HM66AQB36104/18204/9404/8404
Notes: 1. 2. 3. 4. 5. 6. 7. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . AC load current is higher than the shown DC values. AC I/O curves are available upon request. HSTL outputs meet JEDEC HSTL Class I and Class II standards. Measured at VOH = VDDQ/2 Measured at VOL = VDDQ/2 Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching with a tolerance of 10% is 250 typical. The total external capacitance of ZQ ball must be less than 7.5 pF. 8. 0 VIN VDDQ for all input balls (except VREF, ZQ ball) 9. 0 VOUT VDDQ, output disabled. 10. VDDQ = 1.5 V 0.1 V
Capacitance (Ta = +25C, f = 1.0 MHz, VDD = 1.8 V)
Parameter Input capacitance Clock input capacitance Input/output capacitance (D, Q) Symbol CIN CCLK CI/O Min Typ 4 5 6 Max 5 6 7 Unit pF pF pF Test conditions VIN = 0 V VCLK = 0 V VI/O = 0 V
Notes: 1. These parameters are sampled and not 100% tested. 2. Parameters tested with RQ = 250 and VDDQ = 1.5 V.
Rev.0.2, Jan. 2003, page 15 of 31
HM66AQB36104/18204/9404/8404
AC Characteristics (Ta = 0 to +70C, VDD = 1.8 V 0.1 V)
Test Conditions Input waveform (Rise/fall time 0.3 ns)
1.25 V 0.75 V 0.25 V Test points 0.75 V
Output waveform
VDDQ/2
Test points
VDDQ/2
Output load condition
VDDQ/2 0.75 V VREF Zo = 50 SRAM Q 250 ZQ 50
Rev.0.2, Jan. 2003, page 16 of 31
HM66AQB36104/18204/9404/8404
Operating Conditions
Parameter Input high voltage Input low voltage Notes: 1. 2. Symbol VIH (AC) VIL (AC) Min VREF + 0.2 Typ Max VREF - 0.2 Unit V V Notes 1, 2, 3 1, 2, 3
3.
All voltages referenced to VSS (GND). Overshoot: VIH (AC) VDD + 0.7 V for t tKHKH/2 Undershoot: VIL (AC) -0.5 V for t tKHKH/2 Power-up: VIH VDDQ + 0.3 V and VDD 1.7 V and VDDQ 1.4 V for t 200 ms During normal operation, VDDQ must not exceed VDD. R and W signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min). To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC).
Rev.0.2, Jan. 2003, page 17 of 31
HM66AQB36104/18204/9404/8404
HM66AQB36104/HM66AQB18204 HM66AQB9404/HM66AQB8404 -30 Parameter Symbol Min 3.00 Max 3.47 -33 Min 3.30 Max 4.20 -40 Min 4.00 Max 5.25 -50 Min 5.00 Max 6.30 -60 Min 6.00 Max 7.88 Unit Notes ns
Average clock tKHKH cycle time (K, K, C, C) Clock phase jitter (K, K, C, C) tKC var
0.20
0.20
0.20
0.20
0.20
ns
3
Clock high time tKHKL (K, K, C, C) Clock low time tKLKH (K, K, C, C) Clock to clock tKH/KH (K to K, C to C) Clock to clock t/KHKH (K to K, C to C) Clock to data tKHCH clock (K to C, K to C) DLL lock time (K, C)
1.20 1.20 1.35 1.35 0
1.30
1.32 1.32 1.49 1.49 0
1.45
1.60 1.60 1.80 1.80 0
1.80
2.00 2.00 2.20 2.20 0
2.30
2.40 2.40 2.70 2.70 0
2.80
ns ns ns ns ns
tKC lock 1,024 0.45
1,024 30 0.45
1,024 30 0.45
1,024 30 0.45
1,024 30 0.50
Cycle 2 ns ns ns ns
K static to DLL tKC reset 30 reset C, C high to output valid C, C high to output hold C, C high to echo clock valid tCHQV tCHQX tCHCQV
-0.45 0.45
-0.45 0.45
-0.45 0.45
-0.45 0.45
-0.50 0.50
C, C high to tCHCQX echo clock hold CQ, CQ high to tCQHQV output valid CQ, CQ high to tCQHQX output hold C high to output high-Z C high to output low-Z tCHQZ tCHQX1
-0.45 0.25
-0.45 0.27
-0.45 0.30
-0.45 0.35
-0.50 0.40
ns ns ns ns ns 4 4 5 5
-0.25 0.45
-0.27 0.45
-0.30 0.45
-0.35 0.45
-0.40 0.50
-0.45
-0.45
-0.45
-0.45
-0.50
Rev.0.2, Jan. 2003, page 18 of 31
HM66AQB36104/18204/9404/8404
HM66AQB36104/HM66AQB18204 HM66AQB9404/HM66AQB8404 -30 Parameter Symbol Min 0.40 0.40 Max -33 Min 0.40 0.40 Max -40 Min 0.50 0.50 Max -50 Min 0.60 0.60 Max -60 Min 0.70 0.70 Max Unit Notes ns ns 1 1
Address valid tAVKH to K rising edge Control inputs tIVKH valid to K rising edge Data-in valid to tDVKH K, K rising edge K rising edge to tKHAX address hold K rising edge to tKHIX control inputs hold tKHDX K, K rising edge to data-in hold
0.28
0.30
0.35
0.40
0.50
ns
1
0.40 0.40

0.40 0.40

0.50 0.50

0.60 0.60

0.70 0.70

ns ns
1 1
0.28
0.30
0.35
0.40
0.50
ns
1
Notes: 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 2. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. It is recommended that the device is kept inactive during these cycles. 3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations. 5. Transitions are measured 100 mV from steady-state voltage. 6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQZ less than tCHQV. Remarks: 1. This parameter is sampled. 2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 3. Control input signals may not be operated with pulse widths less than tKHKL (min). 4. If C, C are tied high, K, K become the references for C, C timing parameters. 5. VDDQ is +1.5 V DC.
Rev.0.2, Jan. 2003, page 19 of 31
HM66AQB36104/18204/9404/8404
Timing Waveforms
Read and Write Timing
NOP READ WRITE READ WRITE NOP
1
2
3
4
5
6
7
K
K R
tKHKL tKLKH
tKHKH
tKH/KH t/KHKH
tIVKH
tKHIX
tIVKH
tKHIX
W
Address tAVKH Data in
A0 tKHAX
A1
A2 tDVKH tKHDX
A3 tDVKH tKHDX
D10
D11
D12
D13
D30
D31
D32
D33
Data out
Qx2
Qx3
Q00
Q01
tCHQX
Q02
Q03
Q20
Q21
Q22
Q23
tCHQX1 CQ tCHCQX tCHCQV
tCHQX
tCHQV tCHQV
tCQHQV tCQHQX
tCHQZ
CQ
tKHCH
tCHCQX tCHCQV
C tKHKL tKLKH tKHKH tKH/KH t/KHKH
C
tKHCH
Notes: 1. Q00 refers to output from address A0 + 0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1. 2. Outputs are disable (high-Z) one clock cycle after a NOP. 3. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11. Write data is forwarded immediately as read results.
Rev.0.2, Jan. 2003, page 20 of 31
HM66AQB36104/18204/9404/8404
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1k resistor. TDO should be left unconnected.
Test Access Port (TAP) Pins
Symbol I/O TCK TMS TDI Pin assignments 2R 10R 11R Description Test clock input. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. Test mode select. This is the command input for the TAP controller state machine. Test data input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. Test data output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
TDO
1R
Note: The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP.
Rev.0.2, Jan. 2003, page 21 of 31
HM66AQB36104/18204/9404/8404
TAP DC Operating Characteristics (Ta = 0 to +70C, VDD = 1.8 V 0.1 V)
Parameter Input high voltage Input low voltage Input leakage current Output leakage current Output low voltage Symbol VIH VIL ILI ILO VOL1 VOL2 Output high voltage VOH1 VOH2 Min 1.3 -0.3 -5.0 -5.0 1.6 1.4 Max VDD + 0.3 +0.5 +5.0 +5.0 0.2 0.4 Unit V V A A V V V V 0 V VIN VDD 0 V VIN VDD, output disabled IOLC = 100 A IOLT = 2 mA |IOHC| = 100 A |IOHT| = 2 mA Conditions
Notes: 1. All voltages referenced to VSS (GND). 2. Power-up: VIH VDDQ + 0.3 V and VDD +1.7 V and VDDQ +1.4 V for t 200 ms 3. In "EXTEST" mode and "SAMPLE" mode, VDDQ is nominally 1.5 V.
Rev.0.2, Jan. 2003, page 22 of 31
HM66AQB36104/18204/9404/8404
TAP AC Test Condition
* Temperature * Input timing measurement reference levels * Input pulse levels * Input rise/fall time * Output timing measurement reference levels * Test load termination supply voltage (VTT) * Output load Input waveform
1.8 V 0.9 V 0V Test points 0.9 V
0C Ta +70C 0.9 V 0 V to 1.8 V 1.0 ns 0.9 V 0.9 V See figures
Output waveform
0.9 V
Test points
0.9 V
Output load
VTT = 0.9 V
50 Zo = 50 TDO 20 pF
External load at test
Rev.0.2, Jan. 2003, page 23 of 31
HM66AQB36104/18204/9404/8404
TAP AC Operating Characteristics (Ta = 0 to +70C, VDD = 1.8 V 0.1 V)
Parameter Test clock cycle time Test clock high pulse width Test clock low pulse width Test mode select setup Test mode select hold Capture setup Capture hold TDI valid to TCK high TCK high to TDI invalid TCK low to TDO unknown TCK low to TDO valid Note: Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tCS tCH tDVTH tTHDX tTLQX tTLQV Min 100 40 40 10 10 10 10 10 10 0 Max 20 Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 Note
1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
TAP Controller Timing Diagram
tTHTH TCK tMVTH TMS tTHMX TDI tTHDX TDO tCS RAM ADDRESS tCH tTLQX tTLQV tDVTH tTHTL tTLTH
Test Access Port Registers
Register name Instruction register Bypass register ID register Boundary scan register Length 3 bits 1 bit 32 bits 109 bits Symbol IR [2:0] BP ID [31:0] BS [109:1]
Rev.0.2, Jan. 2003, page 24 of 31
HM66AQB36104/18204/9404/8404
TAP Controller Instruction Set
IR2 0 IR1 0 IR0 0 Instruction EXTEST Description The EXTEST instruction allows circuitry external to the component package to be tested. Boundary scan register cells at output balls are used to apply test vectors, while those at input balls capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the Update-IR state of EXTEST, the output drive is turned on and the PRELOAD data is driven onto the output balls. The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO balls in shiftDR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z, except CQ, CQ ball) and the boundary register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. These instructions are not implemented but are reserved for future use. Do not use these instructions. When the SAMPLE instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to SAMPLE metastable input will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO balls. Notes 1, 2
0
0
1
IDCODE
0
1
0
SAMPLE-Z
0 1
1 0
1 0
RESERVED SAMPLE (-PRELOAD)
1 1 1
0 1 1
1 0 1
RESERVED RESERVED BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
Notes: 1. Data in output register is not guaranteed if EXTEST instruction is loaded. 2. After performing EXTEST, power-up conditions are required in order to return part to normal operation.
Rev.0.2, Jan. 2003, page 25 of 31
HM66AQB36104/18204/9404/8404
ID Register
Part
HM66AQB36104 HM66AQB18204 HM66AQB9404 HM66AQB8404
Revision number (31:29)
000 000 000 000
Type number (28:12)
00010011010101010 00010010010101010 00010000010101010 00010001010101010
Vendor JEDEC code (11:1)
00000000111 00000000111 00000000111 00000000111
Start bit (0)
1 1 1 1
Rev.0.2, Jan. 2003, page 26 of 31
HM66AQB36104/18204/9404/8404
Boundary Scan Order
Signal names Bit # Ball ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E x8 C C SA SA SA SA SA SA SA NC NC NC NC NC NC NC NC Q0 D0 NC NC NC NC NC NC Q1 D1 ZQ NC NC NC NC NC NC Q2 x9 C C SA SA SA SA SA SA SA Q8 D8 NC NC NC NC NC NC Q0 D0 NC NC NC NC NC NC Q1 D1 ZQ NC NC NC NC NC NC Q2 x18 C C SA SA SA SA SA SA SA Q0 D0 NC NC Q1 D1 NC NC Q2 D2 NC NC Q3 D3 NC NC Q4 D4 ZQ NC NC Q5 D5 NC NC Q6 x36 C C SA SA SA SA SA SA SA Q0 D0 D9 Q9 Q1 D1 D10 Q10 Q2 D2 D11 Q11 Q3 D3 D12 Q12 Q4 D4 ZQ D13 Q13 Q5 D5 D14 Q14 Q6 Bit # Ball ID 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D Signal names x8 D2 NC NC NC NC NC NC Q3 D3 NC NC CQ SA SA SA SA NC R NC NW0 K K NC NW1 W SA SA SA VSS CQ NC NC NC NC NC x9 D2 NC NC NC NC NC NC Q3 D3 NC NC CQ SA SA SA SA NC R NC BW K K NC NC W SA SA SA VSS CQ NC NC NC NC NC x18 D6 NC NC Q7 D7 NC NC Q8 D8 NC NC CQ NC SA SA SA NC R NC BW0 K K NC BW1 W SA SA SA VSS CQ Q9 D9 NC NC Q10 x36 D6 D15 Q15 Q7 D7 D16 Q16 Q8 D8 D17 Q17 CQ NC SA SA SA NC R BW1 BW0 K K BW3 BW2 W SA SA NC VSS CQ Q18 D18 D27 Q27 Q19
Rev.0.2, Jan. 2003, page 27 of 31
HM66AQB36104/18204/9404/8404
Signal names Bit # Ball ID 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H 1J 2J 3K 3J 2K x8 NC NC NC Q4 D4 NC NC NC NC NC NC Q5 D5 DOFF NC NC NC NC NC x9 NC NC NC Q4 D4 NC NC NC NC NC NC Q5 D5 DOFF NC NC NC NC NC x18 D10 NC NC Q11 D11 NC NC Q12 D12 NC NC Q13 D13 DOFF NC NC Q14 D14 NC x36 D19 D28 Q28 Q20 D20 D29 Q29 Q21 D21 D30 Q30 Q22 D22 DOFF D31 Q31 Q23 D23 D32 Bit # Ball ID 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R
Signal names x8 Q6 D6 NC NC NC NC NC NC Q7 D7 NC NC SA SA SA SA SA SA x9 Q6 D6 NC NC NC NC NC NC Q7 D7 NC NC SA SA SA SA SA SA x18 Q15 D15 NC NC Q16 D16 NC NC Q17 D17 NC NC SA SA SA SA SA SA x36 Q24 D24 D33 Q33 Q25 D25 D34 Q34 Q26 D26 D35 Q35 SA SA SA SA SA SA
90 1K NC NC NC Q32 Note: In boundary scan mode, 1. Clock balls (K / K, C / C) are referenced to each other and must be at opposite logic levels for reliable operation. 2. CQ and CQ data are synchronized to the respective C and C. 3. If C and C tied high, CQ is generated with respect to K and CQ is generated with respect to K.
INTER- INTER- INTER- INTERNAL NAL NAL NAL
Rev.0.2, Jan. 2003, page 28 of 31
HM66AQB36104/18204/9404/8404
TAP Controller State Diagram
1
Test-LogicReset 0
0
Run-Test/ Idle
1
SelectDR-Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0
1
SelectIR-Scan 0 1 Capture-IR 0 0 Shift-IR 1
1
0 1
1
Exit1-IR 0 0 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0
0
Notes: The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK.
Rev.0.2, Jan. 2003, page 29 of 31
HM66AQB36104/18204/9404/8404
Package Dimensions
HM66AQB36104/18204/9404/8404BP (BP-165A)
Preliminary
Unit: mm
15.00 0.20
14 x 1.00
165 x 0.50 0.05
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 10 x 1.00
17.00 0.20
0.25 C
C
0.40 0.06
0.10 C
1.44 0.10
Hitachi Code JEDEC JEITA Mass (reference value)
BP-165A - - -
Rev.0.2, Jan. 2003, page 30 of 31
HM66AQB36104/18204/9404/8404
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Sales Offices
Hitachi, Ltd.
Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
http://www.hitachisemiconductor.com/
For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Europe GmbH Electronic Components Group Dornacher Str 3 D-85622 Feldkirchen Postfach 201, D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-6538-6533/6538-8577 Fax : <65>-6538-6933/6538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://semiconductor.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk
Copyright (c) Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
Colophon 7.0
Rev.0.2, Jan. 2003, page 31 of 31

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